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final publication# 14727 rev: f amendment/ +2 issue date: january 1998 AM28F020 2 megabit (256 k x 8-bit) cmos 12.0 volt, bulk erase flash memory distinctive characteristics n high performance access times as fast as 70 ns n cmos low power consumption 30 ma maximum active current 100 a maximum standby current no data retention power consumption n compatible with jedec-standard byte-wide 32-pin eprom pinouts 32-pin pdip 32-pin plcc 32-pin tsop n 10,000 write/erase cycles minimum n write and erase voltage 12.0 v 5% n latch-up protected to 100 ma from C1 v to v cc +1 v n flasherase electrical bulk chip erase one second typical chip erase time n flashrite programming 10 s typical byte program time 4 s typical chip program time n command register architecture for microprocessor/microcontroller compatible write interface n on-chip address and data latches n advanced cmos flash memory technology low cost single transistor memory cell n automatic write/erase pulse stop timer general description the AM28F020 is a 2 megabit flash memory orga- nized as 256 kbytes of 8 bits each. amds flash mem- ories offer the most cost-effective and reliable read/ write non-volatile random access memory. the AM28F020 is packaged in 32-pin pdip, plcc, and tsop versions. it is designed to be reprogrammed and erased in-system or in standard eprom programmers. the AM28F020 is erased when shipped from the factory. the standard AM28F020 offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus conten- tion, the device has separate chip enable (ce#) and output enable (oe#) controls. amds flash memories augment eprom functionality with in-circuit electrical erasure and programming. the AM28F020 uses a command register to manage this functionality, while maintaining a jedec-standard 32- pin pinout. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. amds flash technology reliably stores memory con- tents even after 10,000 erase and program cycles. the amd cell is designed to optimize the erase and pro- gramming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the AM28F020 uses a 12.0 5% v pp supply input to perform the flasherase and flashrite functions. the highest degree of latch-up protection is achieved with amds proprietary non-epi process. latch-up pro- tection is provided for stresses up to 100 ma on address and data pins from C1 v to v cc +1 v. the AM28F020 is byte programmable using 10 s programming pulses in accordance with amds flashrite programming algorithm. the typical room temperature programming time of the AM28F020 is four seconds. the entire chip is bulk erased using 10 ms erase pulses according to amds flasherase algorithm. typical erasure at room temperature is accomplished in less than one second. the windowed package and the 15C20 minutes required for eprom erasure using ultraviolet light are eliminated. commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine, which controls the erase and programming circuitry. during write cycles, the command register internally latches
2 AM28F020 addresses and data needed for the programming and erase operations. for system design simplification, the AM28F020 is designed to support either we# or ce# controlled writes. during a system write cycle, addresses are latched on the falling edge of we# or ce#, whichever occurs last. data is latched on the rising edge of we# or ce#, whichever occurs first. to simplify discussion, the we# pin is used as the write cycle control pin throughout the rest of this data sheet. all setup and hold times are with respect to the we# signal. amds flash technology combines years of eprom and eeprom experience to produce the highest levels of quality, reliability, and cost effectiveness. the AM28F020 electrically erases all bits simultaneously using fowler-nordheim tunneling. the bytes are pro- grammed one byte at a time using the eprom programming mechanism of hot electron injection. product selector guide block diagram family part number AM28F020 speed options (v cc = 5.0 v 10%) -70 -90 -120 -150 -200 max access time (ns) 70 90 120 150 200 ce # (e # ) access (ns) 70 90 120 150 200 oe # (g # ) access (ns) 35 35 50 55 55 14727f-1 erase voltage switch input/output buffers data latch y-gating 2,097,152 bit cell matrix x-decoder y-decoder chip enable output enable logic program/erase pulse timer low v cc detector command register we# ce# oe# a0Ca17 dq0Cdq7 v cc v ss address latch state control v pp to array program voltage switch
AM28F020 3 connection diagrams v pp v cc dq0 a5 a12 a14 1 3 5 7 9 11 12 10 2 4 8 6 32 30 28 26 24 14 21 23 31 29 25 27 a15 a7 13 22 20 19 a6 15 16 18 17 a4 a3 a2 a1 a0 dq1 dq2 v ss we # (w # ) a13 a8 a9 a11 oe # (g # ) a10 ce # (e # ) dq7 dq6 dq5 dq4 dq3 14727f-2 pdip note : pin 1 is marked for orientation. a16 a17 dq6 v pp dq5 dq4 dq3 1 31 30 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# (g#) a10 ce# (e#) dq7 a12 a15 a16 v cc we# (w#) a17 dq1 dq2 v ss plcc 14727f-3
4 AM28F020 connection diagrams (continued) logic symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tsop 32-pin tsopstandard pinout a11 a9 a8 a13 a14 a17 we # v cc v pp a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe # a10 ce # d7 d6 d5 d4 d3 v ss d2 d1 d0 a0 a1 a2 a3 32-pin tsopreverse pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 a14 a17 we # v cc v pp a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe # a10 ce # d7 d6 d5 d4 d3 v ss d2 d1 d0 a0 a1 a2 a3 14727f-4 18 8 dq0Cdq7 a0Ca17 ce # (e) oe# (g#) we# (w#) 14727f-5
AM28F020 5 ordering information standard products amd standard products are available in several packages and operating ranges. the ordering number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be support- ed in volume for this device. consult the local amd sales of- fice to confirm availability of specific valid combinations and to check on newly released combinations. device number/description AM28F020 2 megabit (256 k x 8-bit) cmos flash memory AM28F020 -70 j c optional processing blank = standard processing b = burn-in contact an amd representative for more information. temperature range c = commercial (0c to +70c) i = industrial (C40c to +85c) e = extended (C55c to +125c) package type p = 32-pin plastic dip (pd 032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) speed option see product selector guide and valid combinations b valid combinations AM28F020-70 pc, pi, pe, jc, ji, je, ec, ei, ee, fc, fi, fe AM28F020-90 AM28F020-120 AM28F020-150 AM28F020-200
6 AM28F020 pin description a0Ca17 address inputs for memory locations. internal latches hold addresses during write cycles. ce # (e # ) chip enable active low input activates the chips control logic and input buffers. chip enable high will deselect the device and operates the chip in stand-by mode. dq0Cdq7 data inputs during memory write cycles. internal latches hold data during write cycles. data outputs during memory read cycles. nc no connect-corresponding pin is not connected internally to the die. oe # (g # ) output enable active low input gates the outputs of the device through the data buffers during memory read cycles. output enable is high during command sequencing and program/erase operations. v cc power supply for device operation. (5.0 v 5% or 10%) v pp program voltage input. v pp must be at high voltage in order to write to the command register. the command register controls all functions required to alter the memory array contents. memory contents cannot be altered when v pp v cc +2 v. v ss ground we # (w # ) write enable active low input controls the write function of the command register to the memory array. the target address is latched on the falling edge of the write enable pulse and the appropriate data is latched on the rising edge of the pulse. write enable high inhibits writing to the device.
AM28F020 7 basic principles the device uses 100% ttl-level control inputs to manage the command register. erase and repro- gramming operations use a fixed 12.0 v 5% high voltage input. read only memory without high v pp voltage, the device functions as a read only memory and operates like a standard eprom. the control inputs still manage traditional read, standby, output disable, and auto select modes. command register the command register is enabled only when high volt- age is applied to the v pp pin. the erase and repro- gramming operations are only accessed via the register. in addition, two-cycle commands are required for erase and reprogramming operations. the tradi- tional read, standby, output disable, and auto select modes are available via the register. the devices command register is written using stan- dard microprocessor write timings. the register con- trols an internal state machine that manages all device operations. for system design simplification, the de- vice is designed to support either we# or ce# con- trolled writes. during a system write cycle, addresses are latched on the falling edge of we# or ce# which- ever occurs last. data is latched on the rising edge of we# or ce# whichever occur first. to simplify the fol- lowing discussion, the we# pin is used as the write cycle control pin throughout the rest of this text. all setup and hold times are with respect to the we# sig- nal. overview of erase/program operations flasherase? sequence a multiple step command sequence is required to erase the flash device (a two-cycle erase command and repeated one cycle verify commands). note: the flash memory array must be completely programmed to 0s prior to erasure. refer to the flashrite? programming algorithm. 1. erase setup: write the setup erase command to the command register. 2. erase: write the erase command (same as setup erase command) to the command register again. the second command initiates the erase operation. the system software routines must now time-out the erase pulse width (10 ms) prior to issuing the erase-verify command. an integrated stop timer prevents any possibility of overerasure. 3. erase-verify: write the erase-verify command to the command register. this command terminates the erase operation. after the erase operation, each byte of the array must be verified. address in- formation must be supplied with the erase-verify command. this command verifies the margin and outputs the addressed byte in order to compare the array data with ffh data (byte erased). after successful data verification the erase-verify command is written again with new address infor- mation. each byte of the array is sequentially veri- fied in this manner. if data of the addressed location is not verified, the erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times. flashrite programming sequence a three step command sequence (a two-cycle program command and one cycle verify command) is required to program a byte of the flash array. refer to the flash- rite algorithm. 1. program setup: write the setup program com- mand to the command register. 2. program: write the program command to the com- mand register with the appropriate address and data. the system software routines must now time- out the program pulse width (10 s) prior to issuing the program-verify command. an integrated stop timer prevents any possibility of overprogramming. 3. program-verify: write the program-verify com- mand to the command register. this command ter- minates the programming operation. in addition, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. after suc- cessful data verification, the programming se- quence is initiated again for the next byte address to be programmed. if data is not verified successfully, the program se- quence is repeated until a successful comparison is verified or the sequence is repeated 25 times. data protection the device is designed to offer protection against acci- dental erasure or programming caused by spurious system level signals that may exist during power transi- tions. the device powers up in its read only state. also, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to pre- vent inadvertent write cycles resulting fromv cc power- up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the device locks out write cycles for
8 AM28F020 v cc < v lko (see dc characteristics section for voltages). when v cc < v lko , the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. the device ignores all writes until v cc > v lko . the user must ensure that the control pins are in the correct logic state when v cc > v lko to prevent uninitentional writes. write pulse glitch protection noise pulses of less than 10 ns (typical) on oe#, ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit power-up of the device with we# = ce# = v il and oe# = v ih will not accept commands on the rising edge of we#. the internal state machine is automat- ically reset to the read mode on power-up. functional description description of user modes table 1. AM28F020 device bus operations legend: x = dont care, where dont care is either v il or v ih levels. v ppl = v pp v cc + 2 v. see dc characteristics for voltage levels of v pph . 0 v < an < v cc + 2 v, (normal ttl or cmos input levels, where n = 0 or 9). notes: 1. v ppl may be grounded, connected with a resistor to ground, or < v cc + 2.0 v. v pph is the programming voltage specified for the device. refer to the dc characteristics. when v pp = v ppl , memory contents can be read but not written or erased. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 2. 3. 11.5 < v id < 13.0 v. minimum v id rise time and fall time (between 0 and v id voltages) is 500 ns. 4. read operation with v pp = v pph may access array data or the auto select codes. 5. with v pp at high voltage, the standby current is i cc + i pp (standby). 6. refer to table 3 for valid d in during a write operation. 7. all inputs are dont care unless otherwise stated, where dont care is either v il or v ih levels. in the auto select mode all addresses except a9 and a0 must be held at v il . 8. if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the am28f010 has a v pp rise time and fall time specification of 500 ns minimum. operation ce # (e # )oe # (g # )we # (w # ) v pp (note 1) a0 a9 i/o read-only read v il v il xv ppl a0 a9 d out standby v ih xxv ppl x x high z output disable v il v ih v ih v ppl x x high z auto-select manufacturer code (note 2) v il v il v ih v ppl v il v id (note 3) code (01h) auto-select device code (note 2) v il v il v ih v ppl v ih v id (note 3) code (2ah) read/write read v il v il v ih v pph a0 a9 d out (note 4) standby (note 5) v ih xxv pph x x high z output disable v il v ih v ih v pph x x high z write v il v ih v il v pph a0 a9 d in (note 6)
AM28F020 9 read only mode when v pp is less than v cc + 2 v, the command register is inactive. the device can either read array or autose- lect data, or be standby mode. read the device functions as a read only memory when v pp < v cc + 2 v. the device has two control functions. both must be satisfied in order to output data. ce# controls power to the device. this pin should be used for spe- cific device selection. oe# controls the device outputs and should be used to gate data to the output pins if a device is selected. address access time t acc is equal to the delay from stable addresses to valid output data. the chip enable access time t ce is the delay from stable addresses and stable ce# to valid data at the output pins. the output enable access time is the delay from the falling edge of oe# to valid data at the output pins (assuming the ad- dresses have been stable at least t acc Ct oe ). standby mode the device has two standby modes. the cmos standby mode (ce# input held at v cc 0.5 v), con- sumes less than 100 a of current. ttl standby mode (ce# is held at v ih ) reduces the current requirements to less than 1ma. when in the standby mode the out- puts are in a high impedance state, independent of the oe# input. if the device is deselected during erasure, program- ming, or program/erase verification, the device will draw active current until the operation is terminated. output disable output from the device is disabled when oe# is at a logic high level. when disabled, output pins are in a high impedance state. auto select flash memories can be programmed in-system or in a standard prom programmer. the device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. alternatively, the device may initially be programmed in a prom programmer prior to soldering the device to the board. the auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. this mode is intended for the purpose of automatically matching the device to be pro- grammed with its corresponding programming algo- rithm. this mode is functional over the entire temperature range of the device. programming in a prom programmer to activate this mode, the programming equipment must force v id (11.5 v to 13.0 v) on address a9. two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all other address lines must be held at v il , and v pp must be less than or equal to v cc + 2.0 v while using this auto select mode. byte 0 (a0 = v il ) represents the manufac- turer code and byte 1 (a0 = v ih ) the device identifier code. for the device these two bytes are given in table 2 of the device data sheet. all identifiers for manufac- turer and device codes will exhibit odd parity with the msb (dq7) defined as the parity bit. table 2. AM28F020 auto select code ty p e a0 code (hex) manufacturer code v il 01 device code v ih 2a
10 AM28F020 erase, program, and read mode when v pp is equal to 12.0 v 5%, the command reg- ister is active. all functions are available. that is, the device can program, erase, read array or autoselect data, or be standby mode. write operations high voltage must be applied to the v pp pin in order to activate the command register. data written to the reg- ister serves as input to the internal state machine. the output of the state machine determines the operational function of the device. the command register does not occupy an addressable memory location. the register is a latch that stores the command, along with the address and data information needed to execute the command. the register is written by bringing we# and ce# to v il , while oe# is at v ih . addresses are latched on the falling edge of we#, while data is latched on the rising edge of the we# pulse. standard microprocessor write timings are used. the device requires the oe# pin to be v ih for write op- erations. this condition eliminates the possibility for bus contention during programming operations. in order to write, oe# must be v ih , and ce# and we# must be v il . if any pin is not in the correct state a write command will not be executed. refer to ac write characteristics and the erase/pro- gramming waveforms for specific timing parameters. command definitions the contents of the command register default to 00h (read mode) in the absence of high voltage applied to the v pp pin. the device operates as a read only mem- ory. high voltage on the v pp pin enables the command register. device operations are selected by writing spe- cific data codes into the command register. table 3 de- fines these register commands. read command memory contents can be accessed via the read com- mand when v pp is high. to read from the device, write 00h into the command register. standard microproces- sor read cycles access data from the memory. the de- vice will remain in the read mode until the command register contents are altered. the command register defaults to 00h (read mode) upon v pp power-up. the 00h (read mode) register de- fault helps ensure that inadvertent alteration of the memory contents does not occur during the v pp power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. table 3. AM28F020 command definitions notes: 1. bus operations are defined in table 1. 2. ra = address of the memory location to be read. ea = address of the memory location to be read during erase-verify. pa = address of the memory location to be programmed. x = dont care. addresses are latched on the falling edge of the we # pulse. 3. rd = data read from location ra during read operation. evd = data read from location ea during erase-verify. pd = data to be programmed at location pa. data latched on the rising edge of we # . pvd = data read from location pa during program-verify. pa is latched on the program command. 4. refer to the appropriate section for algorithms and timing diagrams. command (note 4) first bus cycle second bus cycle operation (note 1) address (note 2) data (note 3) operation (note 1) address (note 2) data (note 3) read memory write x 00h/ffh read ra rd read auto select write x 80h or 90h read 00h/01h 01h/2ah erase setup/erase write write x 20h write x 20h erase-verify write ea a0h read x evd program setup/program write x 40h write pa pd program-verify write x c0h read x pvd reset write x ffh write x ffh
AM28F020 11 flasherase erase sequence erase setup erase setup is the first of a two-cycle erase command. it is a command-only operation that stages the device for bulk chip erase. the array contents are not altered with this command. 20h is written to the command reg- ister in order to perform the erase setup operation. erase the second two-cycle erase command initiates the bulk erase operation. you must write the erase com- mand (20h) again to the register. the erase operation begins with the rising edge of the we# pulse. the erase operation must be terminated by writing a new command (erase-verify) to the register. this two step sequence of the setup and erase com- mands helps to ensure that memory contents are not accidentally erased. also, chip erasure can only occur when high voltage is applied to the v pp pin and all con- trol pins are in their proper state. in absence of this high voltage, memory contents cannot be altered. refer to ac erase characteristics and waveforms for specific timing parameters. note: the flash memory device must be fully programmed to 00h data prior to erasure. this equalizes the charge on all memory cells ensuring reliable erasure. erase-verify command the erase operation erases all bytes of the array in parallel. after the erase operation, all bytes must be sequentially verified. the erase-verify operation is initi- ated by writing a0h to the register. the byte address to be verified must be supplied with the command. ad- dresses are latched on the falling edge of the we# pulse or ce# pulse, whichever occurs later. the rising edge of the we# pulse terminates the erase operation. margin verify during the erase-verify operation, the device applies an internally generated margin voltage to the addressed byte. reading ffh from the addressed byte indicates that all bits in the byte are properly erased. verify next address you must write the erase-verify command with the ap- propriate address to the register prior to verification of each address. each new address is latched on the fall- ing edge of we# or ce# pulse, whichever occurs later. the process continues for each byte in the memory array until a byte does not return ffh data or all the bytes in the array are accessed and verified. if an address is not verified to ffh data, the entire chip is erased again (refer to erase setup/erase). erase verification then resumes at the address that failed to verify. erase is complete when all bytes in the array have been verified. the device is now ready to be pro- grammed. at this point, the verification operation is ter- minated by writing a valid command (e.g. program setup) to the command register. figure 1 and table 4, the flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to per- form electrical erasure. refer to ac erase characteris- tics and waveforms for specific timing parameters.
12 AM28F020 figure 1. flasherase electrical erase algorithm start program all bytes to 00h apply v pph address = 00h plscnt = 0 write erase setup command write erase command time out 10 ms write erase verify time out 6 s read data from device data = ffh last address write reset command apply v ppl erasure completed plscnt = 1000 increment address apply v ppl erase error no ye s no 11559g-6 ye s ye s ye s no no increment plscnt data = 00h
AM28F020 13 flasherase electrical erase algorithm this flash memory device erases the entire array in parallel. the erase time depends on v pp , temperature, and number of erase/program cycles on the device. in general, reprogramming time increases as the number of erase/program cycles increases. the flasherase electrical erase algorithm employs an interactive closed loop flow to simultaneously erase all bits in the array. erasure begins with a read of the mem- ory contents. the device is erased when shipped from the factory. reading ffh data from the device would immediately be followed by executing the flashrite pro- gramming algorithm with the appropriate data pattern. should the device be currently programmed, data other than ffh will be returned from address locations. follow the flasherase algorithm. uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (data = 00h). this is accomplished using the flashrite programming algorithm. erasure then continues with an initial erase operation. erase verification (data = ffh) begins at address 0000h and continues through the array to the last address, or until data other than ffh is encountered. if a byte fails to verify, the device is erased again. with each erase operation, an increasing number of bytes verify to the erased state. typically, devices are erased in less than 100 pulses (one second). erase efficiency may be improved by storing the address of the last byte that fails to verify in a register. following the next erase operation, verification may start at the stored address location. a total of 1000 erase pulses are allowed per reprogram cycle, which corresponds to approximately 10 seconds of cumulative erase time. the entire sequence of erase and byte verification is performed with high voltage applied to the v pp pin. figure 1 illustrates the electrical erase algorithm. table 4. flasherase electrical erase algorithm notes: 1. see ac and dc characteristics for values of v pp parameters. the v pp power supply can be hard-wired to the device or switchable. when v pp is switched, v ppl may be ground, no connect with a resistor tied to ground, or less than v cc + 2.0 v. 2. erase verify is performed only after chip erasure. a final read compare may be performed (optional) after the register is wri tten with the read command. 3. the erase algorithm must be followed to ensure proper and reliable operation of the device. bus operations command comments entire memory must = 00h before erasure (note 3) note: use flashrite programming algorithm (figure 4) for programming. standby wait for v pp ramp to v pph (note 1) initialize: addresses plscnt (pulse count) write erase setup data = 20h erase data = 20h standby duration of erase operation (t whwh2 ) write erase-verify (note 2) address = byte to verify data = a0h stops erase operation standby write recovery time before read = 6 s read read byte to verify erasure standby compare output to ffh increment pulse count write reset data = ffh, reset the register for read operations standby wait for v pp ramp to v ppl (note 1)
14 AM28F020 figure 2. ac waveforms for erase operations analysis of erase timing waveform note: this analysis does not include the requirement to program the entire array to 00h data prior to erasure. refer to the flashrite programming algorithm. erase setup/erase this analysis illustrates the use of two-cycle erase commands (section a and b). the first erase com- mand (20h) is a setup command and does not affect the array data (section a). the second erase com- mand (20h) initiates the erase operation (section b) on the rising edge of this we# pulse. all bytes of the memory array are erased in parallel. no address infor- mation is required. the erase pulse occurs in section c. time-out a software timing routine (10 ms duration) must be ini- tiated on the rising edge of the we# pulse of section b. note: an integrated stop timer prevents any possibil- ity of overerasure by limiting each time-out period of 10 ms. erase-verify upon completion of the erase software timing routine, the microprocessor must write the erase-verify com- mand (a0h). this command terminates the erase oper- ation on the rising edge of the we# pulse (section d). the erase-verify command also stages the device for data verification (section f). after each erase operation each byte must be verified. the byte address to be verified must be supplied with addresses ce # oe # we # data v pp v cc 11559g-7 20h 20h section a0h data out bus cycle write write time-out write time-out read standby command 20h 20h n/a a0h n/a compare data n/a function erase setup erase erase (10 ms) erase- verify transition (6 s) erase verification proceed per erase algorithm ab def cg ab def cg
AM28F020 15 the erase-verify command (section d). addresses are latched on the falling edge of the we# pulse. another software timing routine (6 s duration) must be executed to allow for generation of internal voltages for margin checking and read operation (section e). during erase-verification (section f) each address that returns ffh data is successfully erased. each address of the array is sequentially verified in this manner by re- peating sections d thru f until the entire array is veri- fied or an address fails to verify. should an address location fail to verify to ffh data, erase the device again. repeat sections a thru f. resume verification (section d) with the failed address. each data change sequence allows the device to use up to 1,000 erase pulses to completely erase. typically 100 erase pulses are required. note: all address locations must be programmed to 00h prior to erase. this equalizes the charge on all memory cells and ensures reliable erasure. flashrite programming sequence program setup the device is programmed byte by byte. bytes may be programmed sequentially or at random. program setup is the first of a two-cycle program command. it stages the device for byte programming. the program setup operation is performed by writing 40h to the command register. program only after the program setup operation is completed will the next we# pulse initiate the active programming operation. the appropriate address and data for pro- gramming must be available on the second we# pulse. addresses and data are internally latched on the falling and rising edge of the we# pulse respectively. the ris- ing edge of we# also begins the programming opera- tion. you must write the program-verify command to terminate the programming operation. this two step sequence of the setup and program commands helps to ensure that memory contents are not accidentally written. also, programming can only occur when high voltage is applied to the v pp pin and all control pins are in their proper state. in absence of this high voltage, memory contents cannot be programmed. refer to ac characteristics and waveforms for specific timing parameters. program verify command following each programming operation, the byte just programmed must be verified. write c0h into the command register in order to initiate the program-verify operation. the rising edge of this we pulse terminates the programming operation. the program-verify operation stages the device for verifica- tion of the last byte programmed. addresses were pre- viously latched. no new information is required. margin verify during the program-verify operation, the device applies an internally generated margin voltage to the ad- dressed byte. a normal microprocessor read cycle out- puts the data. a successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed. the original pro- grammed data should be stored for comparison. pro- gramming then proceeds to the next desired byte location. should the byte fail to verify, reprogram (refer to program setup/program). figure 3 and table 5 indi- cate how instructions are combined with the bus oper- ations to perform byte programming. refer to ac programming characteristics and waveforms for spe- cific timing parameters. flashrite programming algorithm the device flashrite programming algorithm employs an interactive closed loop flow to program data byte by byte. bytes may be programmed sequentially or at ran- dom. the flashrite programming algorithm uses 10 s programming pulses. each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. the program al- gorithm allows for up to 25 programming operations per byte per reprogramming cycle. most bytes verify after the first or second pulse. the entire sequence of pro- gramming and byte verification is performed with high voltage applied to the v pp pin. figure 3 and table 5 il- lustrate the programming algorithm.
16 AM28F020 figure 3. flashrite programming algorithm start apply v pph plscnt = 0 write program setup command write program command (a/d) time out 10 s write program verify command time out 6 s read data from device last address write reset command apply v ppl programming completed plscnt = 25? increment address apply v ppl device failed no 11559g-8 ye s ye s no no verify byte increment plscnt ye s
AM28F020 17 table 5. flashrite programming algorithm notes: 1. see ac and dc characteristics for values of v pp parameters. the v pp power supply can be hard-wired to the device or switchable. when v pp is switched, v ppl may be ground, no connect with a resistor tied to ground, or less than v cc + 2.0 v. 2. program verify is performed only after byte programming. a final read/compare may be performed (optional) after the register is written with the read command. bus operations command comments standby wait for v pp ramp to v pph (note 1) initialize pulse counter write program setup data = 40h program valid address/data standby duration of programming operation (t whwh1 ) write program-verify (note 2) data = c0h stops program operation standby write recovery time before read = 6 s read read byte to verify programming standby compare data output to data expected write reset data = ffh, resets the register for read operations. standby wait for v pp ramp to v ppl (note 1)
18 AM28F020 figure 4. ac waveforms for programming operations analysis of program timing waveforms program setup/program two-cycle write commands are required for program operations (section a and b). the first program com- mand (40h) is a setup command and does not affect the array data (section a).the second program com- mand latches address and data required for program- ming on the falling and rising edge of we# respectively (section b). the rising edge of this we# pulse (section b) also initiates the programming pulse. the device is programmed on a byte by byte basis either sequentially or randomly. the program pulse occurs in section c. time-out a software timing routine (10 s duration) must be initi- ated on the rising edge of the we# pulse of section b. note: an integrated stop timer prevents any possibility of overprogramming by limiting each time-out period of 10 s. program-verify upon completion of the program timing routine, the mi- croprocessor must write the program-verify command (c0h). this command terminates the programming op- eration on the rising edge of the we# pulse (section d). the program-verify command also stages the device for data verification (section f). another software timing addresses ce # oe # we # data v pp v cc 11559g-9 data in 20h section a0h data out bus cycle write write time-out write time-out read standby command 40h program address, program data n/a c0h (stops program) n/a compare data n/a function program setup program command latch address and data program (10 s) program verify transition (6 s) program verification proceed per programming algorithm ab def cg a b de f cg
AM28F020 19 routine (6 s duration) must be executed to allow for generation of internal voltages for margin checking and read operations (section e). during program-verification (section f) each byte just programmed is read to compare array data with original program data. when successfully verified, the next de- sired address is programmed. should a byte fail to ver- ify, reprogram the byte (repeat section a thru f). each data change sequence allows the device to use up to 25 program pulses per byte. typically, bytes are verified within one or two pulses. algorithm timing delays there are four different timing delays associated with the flasherase and flashrite algorithms: 1. the first delay is associated with the v pp rise-time when v pp first turns on. the capacitors on the v pp bus cause an rc ramp. after switching on the v pp , the delay required is proportional to the number of devices being erased and the 0.1 mf/device. v pp must reach its final value 100 ns before commands are executed. 2. the second delay time is the erase time pulse width (10 ms). a software timing routine should be run by the local microprocessor to time out the delay. the erase operation must be terminated at the conclu- sion of the timing routine or prior to executing any system interrupts that may occur during the erase operation. to ensure proper device operation, write the erase-verify operation after each pulse. 3. a third delay time is required for each programming pulse width (10 ms). the programming algorithm is interactive and verifies each byte after a program pulse. the program operation must be terminated at the conclusion of the timing routine or prior to exe- cuting any system interrupts that may occur during the programming operation. 4. a fourth timing delay associated with both the flasherase and flashrite algorithms is the write re- covery time (6 ms). during this time internal circuitry is changing voltage levels from the erase/ program level to those used for margin verify and read oper- ations. an attempt to read the device during this pe- riod will result in possible false data (it may appear the device is not properly erased or programmed). note: software timing routines should be written in machine language for each of the delays. code written in machine language requires knowledge of the appro- priate microprocessor clock speed in order to accu- rately time each delay. parallel device erasure many applications will use more t han one flash memory device. total erase time may be minimized by implementing a parallel erase algorithm. flash memories may erase at different rates. therefore each device must be verified separately. when a device is completely erased and verified use a masking code to prevent further erasure. the other devices will continue to erase until verified. the masking code applied could be the read command (00h). power-up/power-down sequence the device powers-up in the read only mode. power supply sequencing is not required. note that if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the device has v pp rise time and fall time specification of 500 ns minimum. reset command the reset command initializes the flash memory de- vice to the read mode. in addition, it also provides the user with a safe method to abort any device operation (including program or erase). the reset command must be written two consecutive times after the setup program command (40h). this will reset the device to the read mode. following any other flash command write the reset command once to the device. this will safely abort any previous operation and initialize the device to the read mode. the setup program command (40h) is the only com- mand that requires a two sequence reset cycle. the first reset command is interpreted as program data. however, ffh data is considered null data during pro- gramming operations (memory cells are only pro- grammed from a logical 1 to 0). the second reset command safely aborts the programming operation and resets the device to the read mode. memory contents are not altered in any case. this detailed information is for your reference. it may prove easier to always issue the reset command two consecutive times. this eliminates the need to deter- mine if you are in the setup program state or not. programming in-system flash memories can be programmed in-system or in a standard prom programmer. the device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. alternatively, the device may initially be programmed in a prom programmer prior to soldering the device to the board.
20 AM28F020 auto select command amds flash memories are designed for use in applica- tions where the local cpu alters memory contents. ac- cordingly, manufacturer and device codes must be accessible while the device resides in the target sys- tem. prom programmers typically access the signa- ture codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not a generally desired system design practice. the device contains an auto select operation to sup- plement traditional prom programming methodology. the operation is initiated by writing 80h or 90h into the command register. following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. a read cycle from address 0001h returns the device code. to terminate the operation, it is necessary to write another valid command, such as reset (ffh), into the register.
AM28F020 21 absolute maximum ratings storage temperature . . . . . . . . . . . . C65 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . C55 c to +125 c voltage with respect to ground all pins except a9 and v pp (note 1) .C2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . C2.0 v to +7.0 v a9, v pp (note 2) . . . . . . . . . . . . . . . C2.0 v to +14.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9 and v pp is C0.5 v. during voltage transitions, a9 and v pp may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 and v pp is +13.0 v, which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ). . . . . . . . . . . .0c to +70c industrial (i) devices ambient temperature (t a ). . . . . . . . . .C40c to +85c extended (e) devices ambient temperature (t a ). . . . . . . . .C55c to +125c v cc supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . +4.50 v to +5.50 v v pp voltages read . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +12.6 v program, erase, and verify . . . . . . +11.4 v to +12.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
22 AM28F020 maximum overshoot maximum negative input overshoot maximum positive input overshoot maximum v pp overshoot 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 14727f-10 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 14727f-11 20 ns 13.5 v v cc + 0.5 v 20 ns 20 ns 14.0 v 14727f-12
AM28F020 23 dc characteristics over operating range unless otherwise specified ttl/nmos compatible notes: 1. caution: the AM28F020 must not be removed from (or inserted into) a socket when v cc or v pp is applied. if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the AM28F020 has a v pp rise time and fall time specification of 500 ns minimum. 2. i cc1 is tested with oe# = v ih to simulate open outputs. 3. maximum active power usage is the sum of i cc and i pp . 4. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input leakage current v cc = v cc max, v in = v cc or v ss 1.0 a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 a i ccs v cc standby current v cc = v cc max, ce # = v ih 0.2 1.0 ma i cc1 v cc active read current v cc = v cc max, ce # = v il, oe # = v ih i out = 0 ma, at 6 mhz 20 30 ma i cc2 v cc programming current ce # = v il programming in progress (note 4) 20 30 ma i cc3 v cc erase current ce # = v il erasure in progress (note 4) 20 30 ma i pps v pp standby current v pp = v ppl 1.0 a i pp1 v pp read current v pp = v pph 70 200 a v pp = v ppl 1.0 i pp2 v pp programming current v pp = v pph programming in progress (note 4) 10 30 ma i pp3 v pp erase current v pp = v pph erasure in progress (note 4) 10 30 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 2.4 v v id a9 auto select voltage a9 = v id 11.5 13.0 v i id a9 auto select current a9 = v id max, v cc = v cc max 5 50 a v ppl v pp during read-only operations note: erase/program are inhibited when v pp = v ppl 0.0 v cc +2.0 v v pph v pp during read/write operations 11.4 12.6 v v lko low v cc lock-out voltage 3.2 3.7 v
24 AM28F020 dc characteristics cmos compatible notes: 1. caution: the AM28F020 must not be removed from (or inserted into) a socket when v cc or v pp is applied. if v cc 1.0 volt, the voltage difference between v pp and v cc should not exceed 10.0 volts. also, the AM28F020 has a v pp rise time and fall time specification of 500 ns minimum. 2. i cc1 is tested with oe # = v ih to simulate open outputs. 3. maximum active power usage is the sum of i cc and i pp . 4. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input leakage current v cc = v cc max, v in = v cc or v ss 1.0 a i lo output leakage current v cc = v cc max, v out = v cc or v ss 1.0 a i ccs v cc standby current v cc = v cc max, ce # = v cc + 0.5 v 15 100 a i cc1 v cc active read current v cc = v cc max, ce # = v il, oe # = v ih i out = 0 ma, at 6 mhz 20 30 ma i cc2 v cc programming current ce # = v il programming in progress (note 4) 20 30 ma i cc3 v cc erase current ce # = v il erasure in progress (note 4) 20 30 ma i pps v pp standby current v pp = v ppl 1.0 a i pp1 v pp read current v pp = v pph 70 200 a i pp2 v pp programming current v pp = v pph programming in progress (note 4) 10 30 ma i pp3 v pp erase current v pp = v pph erasure in progress (note 4) 10 30 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v id a9 auto select voltage a9 = v id 11.5 13.0 v i id a9 auto select current a9 = v id max, v cc = v cc max 5 50 a v ppl v pp during read-only operations note: erase/program are inhibited when v pp = v ppl 0.0 v cc + 2.0 v v pph v pp during read/write operations 11.4 12.6 v v lko low v cc lock-out voltage 3.2 3.7 v
AM28F020 25 figure 5. AM28F020average i cc active vs. frequency vcc = 5.5 v, addressing pattern = minmax data pattern = checkerboard test conditions table 6. test specifications i cc active in ma 30 25 20 15 10 0 0123456789101112 frequency in mhz 14727f-13 C55 c 0 c 25 c 70 c 125 c 5 2.7 k w c l 6.2 k w 5.0 v device under te s t 14727f-14 figure 6. test setup note: diodes are in3064 or equivalent test condition -70 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 10 ns input pulse levels 0.0C3.0 0.45C2.4 v input timing measurement reference levels 1.5 0.8, 2.0 v output timing measurement reference levels 1.5 0.8, 2.0 v
26 AM28F020 switching test waveforms switching characteristics over operating range unless otherwise specified ac characteristicsread-only operations notes: 1. guaranteed by design; not tested. 2. not 100% tested. parameter symbols AM28F020 speed options jedec standard parameter description -70 -90 -120 -150 -200 unit t avav t rc read cycle time (note 2) min 70 90 120 150 200 ns t elqv t ce chip enable accesstime max 70 90 120 150 200 ns t av qv t acc address access time max 70 90 120 150 200 ns t glqv t oe output enable access time max 35 35 50 55 55 ns t elqx t lz chip enable to output in low z (note 2)min00000ns t ehqz t df chip disable to output in high z (note 1) max 20 20 30 35 35 ns t glqx t olz output enable to output in low z (note 2) min 00000ns t ghqz t df output disable to output in high z (note 2) max 20 20 30 35 35 ns t axqx t oh output hold from first of address, ce#, or oe# change (note 2) min00000ns t whgl write recovery time before read min66666s t vcs v cc setup time to valid read (note 2) min 50 50 50 50 50 s 14727f-15 3 v 0 v input output 1.5 v 1.5 v test points ac testing for -70 devices: inputs are driven at 3.0 v for a logic 1 and 0 v for a logic 0. input pulse rise and fall time s are 10 ns. 2.4 v 0.45 v input output test points 2.0 v 2.0 v 0.8 v 0.8 v ac testing (all speed options except -70): inputs are driven at 2.4 v for a logic 1 and 0.45 v for a logic 0. input pulse rise and fall times are 10 ns.
AM28F020 27 ac characteristicswrite (erase/program) operations notes: 1. read timing characteristics during read/write operations are the same as during read-only operations. refer to ac characteristics for read only operations. 2. maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally on the device. 3. chip enable-controlled writes: write operations are driven by the valid combination of chip enable (ce#) and write enable (we#). in systems where ce# defines the write pulse width (within a longer we# timing waveform) all setup, hold and inactive we# times should be measured relative to the ce# waveform. 4. not 100% tested. parameter symbols AM28F020 speed options jedec standard description -70 -90 -120 -150 -200 unit t avav t wc write cycle time (note 4) min 70 90 120 150 200 ns t av wl t as address setup time min 0 0 0 0 0 ns t wlax t ah address hold time min 45 45 50 60 75 ns t dvwh t ds data setup time min 45 45 50 50 50 ns t whdx t dh data hold time min 10 10 10 10 10 ns t whgl t wr write recovery time before read min 6 6 6 6 6 s t ghwl read recovery time before write min 0 0 0 0 0 s t elwl t cs ce # setup time min 0 0 0 0 0 ns t wheh t ch ce # hold time min 0 0 0 0 0 ns t wlwh t wp write pulse width min 45 45 50 60 60 ns t whwl t wph write pulse width high min 20 20 20 20 20 ns t whwh1 duration of programming operation (note 2) min 10 10 10 10 10 s t whwh2 duration of erase operation (note 2) min 9.5 9.5 9.5 9.5 9.5 ms t vpel v pp setup time to chip enable low (note 4) min 100 100 100 100 100 ns t vcs v cc setup time to chip enable low (note 4) min 50 50 50 50 50 s t vppr v pp rise time (note 4) 90% v pph min 500 500 500 500 500 ns t vppf v pp fall time (note 4) 10% v ppl min 500 500 500 500 500 ns t lko v cc < v lko to reset (note 4) min 100 100 100 100 100 ns
28 AM28F020 key to switching waveforms switching waveforms waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) addresses ce# (e#) oe# (g#) we# (w#) data (dq) 5.0 v v cc 0 v power-up, standby device and address selection outputs enabled data valid standby, power-down addresses stable high z high z t whgl t avqv (t acc ) t ehqz (t df ) t ghqz (t df ) t elqx (t lz ) t glqx (t olz ) t elqv (t ce ) t glqv (t oe ) t axqx (t oh ) output valid t avav (t rc ) t vcs figure 7. ac waveforms for read operations 14727f-14
AM28F020 29 switching waveforms figure 8. ac waveforms for erase operations data in = a0h va lid data out erase-verify command erase verification standby, power-down t wlax (t ah ) t ehqz (t df ) t whgl t ghqz (t df ) t glqx (t olz ) t glqv (t oe ) t elqv (t ce ) 14727f-16 t elqx (t lz ) t avav (t rc ) t axqx (t oh ) data in = 20h data in = 20h setup erase command erase command power-up, standby t avw l (t as ) t avav (t wc ) t elwl (t cs ) t ghwl (t oes ) t wheh (t ch ) t whwh2 t whdx (t dh ) t wlwh (t wp ) t dv wh (t ds ) t vcs t vpel addresses high z ce# (e#) oe# (g#) we# (w # ) data (dq) 5.0 v v cc 0 v v pph v pp v ppl erasure t whwl (t wph )
30 AM28F020 switching waveforms figure 9. ac waveforms for programming data in = c0h va lid data out verify command programming verification standby, power-down t wlax (t ah ) t ghqz (t df ) t whgl t ghqz (t df ) t glqx (t olz ) t glqv (t oe ) t elqv (t ce ) 14727f-17 t elqx (t lz ) t avav (t rc ) t axqx (t oh ) data in = 40h data in setup program command program command latch address and data power-up, standby t av wl (t as ) t avav (t wc ) t elwl (t cs ) t ghwl (t oes ) t wheh (t ch ) t whwh1 t whwl (t wph ) t whdx (t dh ) t wlwh (t wp ) t dv wh (t ds ) t vcs t vpel addresses high z ce # (e # ) oe # (g # ) we # (w#) data (dq) 5.0 v v cc 0 v v pph v pp v ppl programming
AM28F020 31 erase and programming performance notes: 1. 25 c, 12 v v pp . 2. maximum time specified is lower than worst case. worst case is derived from the flasherase/flashrite pulse count (flasherase = 1000 max and flashrite = 25 max). typical worst case for program and erase is significantly less than the actual device limit. latchup characteristics pin capacitance note: sampled, not 100% tested. test conditions t a = 25c, f = 1.0 mhz. data retention parameter limits comments min ty p (note 1) max (note 2) unit chip erase time 1 10 sec excludes 00h programming prior to erasure chip programming time 4 25 sec excludes system-level overhead write/erase cycles 10,000 cycles parameter min max input voltage with respect to v ss on all pins except i/o pins (including a9 and v pp ) C1.0 v 13.5 v input voltage with respect to v ss on all pins i/o pins C1.0 v v cc + 1.0 v current C100 ma +100 ma includes all pins except v cc test conditions: v cc = 5.0 v, one pin at a time. parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 8 10 pf c out output capacitance v out = 0 8 12 pf c in2 v pp input capacitance v pp = 0 8 12 pf parameter test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
32 AM28F020 physical dimensions pd03232-pin plastic dip (measured in inches) pl03232-pin plastic leaded chip carrier (measured in inches) pin 1 i.d. 1.640 1.670 .530 .580 .005 min .045 .065 .090 .110 .140 .225 .120 .160 .016 .022 seating plane .015 .060 16-038-s_ag pd 032 ec75 5-28-97 lv 32 17 16 .630 .700 0 10 .600 .625 .009 .015 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
33 AM28F020 physical dimensions ts03232-pin standard thin small outline package (measured in millimeters) pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 3-25-97 lv 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
AM28F020 34 physical dimensions tsr03232-pin reversed thin small outline package (measured in millimeters) 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 3-25-97 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0 5 0.08 0.20
35 AM28F020 datasheet revision summary for AM28F020 revision e+1 distinctive characteristics: high performance: the fastest speed option available is now 70 ns. general description: paragraph 2: changed fastest speed option to 70 ns. product selector guide: added -70, deleted -95 and -250 speed options. ordering information, standard products: the -70 speed option is now listed in the example. valid combinations: added -70, deleted -95 and -250 combinations. operating ranges: v cc supply voltages: added -70, deleted -95 and -250 speed options. ac characteristics: read only operations characteristics: added the -70 column and test conditions. deleted -95 and -250 speed options. ac characteristics: write/erase/program operations: added the -70 col- umn. deleted -95 and -250 speed options. changed speed option in note 2 to -70. switching test waveforms: in the 3.0 v waveform caption, changed -95 to -70. revision f matched formatting to other current data sheets. revision f+1 figure 3, flashrite programming algorithm: moved end of arrow originating from increment address box so that it points to the plscnt = 0 box, not the write pro- gram verify command box. this is a correction to the diagram on page 6-189 of the 1998 flash memory data book. revision f+2 programming in a prom programmer: deleted the paragraph (refer to the auto select paragraph in the erase, program, and read mode section for programming the flash memory de- vice in-system). trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. expressflash is a trademark of advanced micro devices, inc. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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